The Liquid Crystal Display (LCD) possesses advantages of thin body, power saving and no radiation to be widely used in many application scope, such as LCD TV, mobile phone, personal digital assistant (PDA), digital camera, notebook, laptop, and dominates the flat panel display field.
The GOA technology, i.e. the Gate Driver on Array technology utilizes the original array manufacture processes of the liquid crystal display panel to manufacture the driving circuit of the level scan lines on the substrate around the active area, to replace the external Integrated Circuit (IC) for accomplishing the driving of the level scan lines. The GOA technology can reduce the bonding procedure of the external IC and has potential to raise the productivity and lower the production cost. Meanwhile, it can make the liquid crystal display panel more suitable to the narrow frame or non frame design of display products.
With the development of the LTPS semiconductor TFT, the LTPS-TFT LCD also becomes the focus that people pay lots of attentions. Because the LTPS semiconductor has better order than amorphous silicon (a-Si) and the LTPS itself has extremely high carrier mobility which can be more than 100 times of the amorphous silicon semiconductor, which the GOA skill can be utilized to manufacture the gate driver on the TFT array substrate to achieve the objective of system integration and saving the space and the cost of the driving IC.
Please refer to FIG. 1. A GOA circuit based on LTPS semiconductor thin film transistor according to prior art comprises GOA units of a plurality of stages, and n is set to be a positive integer, and the nth stage GOA unit comprises: a first thin film transistor T1, and a gate of the first thin film transistor T1 is electrically coupled to a Mth clock signal CK(M), and a source is electrically coupled to an output end G(n−1) of a former stage n−1th GOA unit, and a drain is electrically coupled to a third node K(n); a second thin film transistor T2, and a gate of the second thin film transistor T2 is electrically coupled to the first node Q(n), and a source is electrically coupled to a M+1th clock signal CK(M+1), and a drain is electrically coupled to an output end G(n); a third thin film transistor T3, and a gate of the third thin film transistor T3 is electrically coupled to a M+2th clock signal CK(M+2), and a drain is electrically coupled to the third node K(n), and a source is electrically coupled to an output end G(n+1) of a latter stage n+1th GOA unit; a fourth thin film transistor T4, and a gate of the fourth thin film transistor T4 is electrically coupled to a M+3th clock signal CK(M+3), and a drain is electrically coupled to the output end G(n), and a source is electrically coupled to a constant low voltage level VGL; a fifth thin film transistor T5, and a gate of the fifth thin film transistor T5 is electrically coupled to a constant high voltage level VGH, and a source is electrically coupled to the third node K(n), and a drain is electrically coupled to the first node Q(n); a sixth thin film transistor T6, a gate of the sixth thin film transistor T6 is electrically coupled to the second node P(n), and a drain is electrically coupled to the third node K(n), and a source is electrically coupled to the constant low voltage level VGL; a seventh thin film transistor T7, and a gate of the seventh thin film transistor T7 is electrically coupled to the second node P(n), and a drain is electrically coupled to the output end G(n), and a source is electrically coupled to the constant low voltage level VGL; an eighth thin film transistor T8, and a gate of the eighth thin film transistor T8 is electrically coupled to the third node K(n), and a drain is electrically coupled to the second node P(n), and a source is electrically coupled to the constant low voltage level VGL; a ninth thin film transistor T9, and both a gate and a source of the ninth thin film transistor T9 are electrically coupled to the M+1th clock signal CK(M+1), and a drain is electrically coupled to the second node P(n); a boost capacitor C1, and one end of the boost capacitor C1 is electrically coupled to the first node Q(n), and the other end is electrically coupled to the output end G(n); a second capacitor C2, and one end of the second capacitor C2 is electrically coupled to second node P(n), and the other end is electrically coupled to the constant low voltage level VGL.
The output unit comprises: a second thin film transistor, and a gate of the second thin film transistor is electrically coupled to the first node, and a source is electrically coupled to a Mth clock signal, and a drain is electrically coupled to an output end; and a bootstrap capacitor, and one end of the bootstrap capacitor is electrically coupled to a first node, and the other end is electrically coupled to the output end; with combination of FIG. 1 and FIG. 2, the forward scan is illustrated, as forward scanning, the working process is: first, Both the Mth clock signal CK(M) and the output end G(n−1) of the former stage n−1th GOA unit provides high voltage level, and the first and the fifth thin film transistors T1, T5 are on, and the firs node Q(n) is pre-charged to high voltage level; then, the Mth clock signal CK(M) and the output end G(n−1) of the former stage n−1th GOA unit drop to be low voltage level, and the M+1th clock signal CK(M+1) provides high voltage level, and the first node Q(n) is held to be high voltage level due to the storage function of the boost capacitor C1, and the second thin film transistor T2 is on, and the output end G(n) outputs the high voltage level of the M+1th clock signal CK(M+1) to raise the first node Q(n) to be higher voltage level, and meanwhile, the eighth thin film transistor T8 is on, and the second node P(n) is pulled down to be the constant low voltage level, and the sixth, seventh thin film transistors T6, T7 are off; then, both the M+2clock signal CK(M+2) and the output end G(n+1) of the latter stage n+1th GOA unit provide high voltage level, and the first node Q(n) is still high voltage level, and the M+1th clock signal CK(M+1) drops to be low voltage level, and the output end G(n) outputs the low voltage of the M+1th clock signal CK(M+1); and then, the Mth clock signal provides high voltage level, again, and the output end G(n−1) of the former stage n−1th GOA unit is held to be low voltage level, and the first thin film transistor T1 is on to pull down the first node Q(n) to be low voltage level, and the eighth thin film transistor T8 is off; thereafter, the M+1th clock signal CK(M+1) provides high voltage level, and the ninth thin film transistor T9 is on, and the second node P(n) is charged to be the high voltage level of the M+1th clock signal CK(M+1), and the sixth, seventh thin film transistors T6, T7 are on to respectively keep pulling down the first node Q(n) and the output end G(n) to the constant low voltage level VGL, and under the function of the second capacitor C2, the second node P(n) is held to be high voltage level, and the sixth, seventh thin film transistors T6, T7 are on to hold the low voltage levels of the first node Q(n) and the output end G(n).
In the aforesaid GOA circuit based on LTPS semiconductor thin film transistor according to prior art, for the GOA unit of any stage, the voltage level of the second node P(n) and the output signal of the output end G(n) are both controlled with the M+1th clock signal CK(M+1), and the first node Q(n) is charged and discharged through the Mth clock signal CK(M) and the M+2th clock signal CK(M+2). Such arrangement will increase the serious delay of the output, and result in the function failure of the GOA circuit.